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WM8739 / WM8739l stereo audio adc wolfson microelectronics plc www.wolfsonmicro.com production data, december 2002, rev 3.1 copyright ? 2002 wolfson microelectronics plc description the WM8739 is a stereo audio adc. the WM8739 is designed specifically for portable mp3 audio and speech players and recorders. the WM8739 is also ideal for md, cd-rwmachines and dat recorders. stereo line-level audio inputs are provided, along with a mute and volume function, and master or slave mode clocking schemes. the device also has a programmable high pass filter to remove residual dc offsets. stereo 24-bit multi-bit sigma delta adcs are used with oversampling digital interpolation and digital filters. digital audio output word lengths from 16-32 bits and sampling rates from 8khz to 96khz are supported. the device is controlled via a 2 or 3 wire serial interface. the interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. the device is available in a 20-pin ssop package or a 28-lead, 5 5mm qfn package. features ? 90db snr (a weighted @ 48khz) adc ? low power - recording: 37mw(WM8739) / 12mw(WM8739l) - standby and powerdown modes down to 1 a ? low supply voltages - 1.8 C 3.6v analogue supply (l version) - 2.7 C 3.6v analogue supply (standard version) - 1.42 C 3.6v digital supply (both versions) ? selectable sample rate: 8khz C 96khz ? selectable adc high pass filter ? 2 or 3-wire mpu serial control interface ? programmable audio data interface modes -i 2 s, left, right justified or dsp - 16/20/24/32 bit word lengths - master or slave clocking mode ? 20-pin ssop or 5x5mm qfn package options applications ? cd, minidisc and dat recorders ? general purpose audio digitisation block diagram vol/ mute vol/ mute adc adc digital filters control interface csb sdin sclk rlinein llinein vmid dbvdd dgnd avdd agnd +12 to -34.5db, 1.5db steps +12to-34.5db, 1.5db steps dcvdd adclrc adcdat div2 xti/mclk xto mode digtal audio interface bclk osc w WM8739
WM8739 / WM8739l production data w pd rev 3.1 december 2002 2 pin configuration (ssop) ordering information (ssop) device avdd range package xWM8739eds 2.7 to 3.6v 20-pin ssop xWM8739eds/r 2.7 to 3.6v 20-pin ssop (tape and reel) WM8739leds 1.8 to 3.6v 20-pin ssop WM8739leds/r 1.8 to 3.6v 20-pin ssop (tape and reel) sdin sclk xti/mclk xto dcvdd dgnd dbvdd bclk dnc dnc csb mode llinein rlinein vmid agnd avdd nc adclrc adcdat 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 note: reel quantity = 2,000 pin description (ssop package) pin name type description 1 sdin digital input 3-wire mpu data input / 2-wire mpu data input 2 sclk digital input 3-wire mpu clock input / 2-wire mpu clock input 3 xti/mclk digital input crystal input or master clock input (mclk) 4 xto digital output crystal output 5 dcvdd supply digital core vdd 6 dgnd ground digital gnd 7 dbvdd supply digital buffers vdd 8 bclk digital input/output digital audio port clock 9dnc testpin do not connect (leave this pin floating) 10 dnc test pin do not connect (leave this pin floating) 11 adcdat digital output adc digital audio data output 12 adclrc digital input/output adc sample rate clock 13 nc no internal connection 14 avdd supply analogue vdd 15 agnd ground analogue gnd 16 vmid analogue output mid-rail reference decoupling point 17 rlinein analogue input right channel line input (ac coupled) 18 llinein analogue input left channel line input (ac coupled) 19 mode digital input control interface selection, pull up (on power up only) 20 csb digital input 3-wire mpu chip select/ 2-wire mpu interface address selection
WM8739 / WM8739l production data w pd rev 3.1 december 2002 3 pin configuration (qfn) ordering information (qfn) device avdd range package WM8739efl 2.7 to 3.6v 28-pin qfn (5x5x0.9 mm) WM8739efl/r 2.7 to 3.6v 28-pin qfn (5x5x0.9 mm) (tape and reel) WM8739lefl 1.8 to 3.6v 28-pin qfn (5x5x0.9 mm) WM8739lefl/r 1.8 to 3.6v 28-pin qfn (5x5x0.9 mm) (tape and reel) nc nc nc adclrc adcdat dnc dnc xti/mclk xto dcvdd dgnd dbvdd nc bclk 28 27 26 25 24 23 22 nc rlinein llinein mode csb sdin sclk 1234567 8 10 9 11 14 13 12 21 20 19 18 17 16 15 nc vmid agnd avdd nc nc nc note: reel quantity = 3,500 pin description (qfn package) pin name type description 1 xti/mclk digital input crystal input or master clock input (mclk) 2 xto digital output crystal output 3 dcvdd supply digital core vdd 4 dgnd ground digital gnd 5 dbvdd supply digital buffers vdd 6nc no internal connection 7 bclk digital input/output digital audio port clock 8, 9 dnc test pin do not connect (leave this pin floating) 10 adcdat digital output adc digital audio data output 11 adclrc digital input/output adc sample rate clock 12 - 17 nc no internal connection 18 avdd supply analogue vdd 19 agnd ground analogue gnd 20 vmid analogue output mid-rail reference decoupling point 21, 22 nc no internal connection 23 rlinein analogue input right channel line input (ac coupled) 24 llinein analogue input left channel line input (ac coupled) 25 mode digital input control interface selection, pull up (on power up only) 26 csb digital input 3-wire mpu chip select/ 2-wire mpu interface address selection 27 sdin digital input 3-wire mpu data input / 2-wire mpu data input 28 sclk digital input 3-wire mpu clock input / 2-wire mpu clock input
WM8739 / WM8739l production data w pd rev 3.1 december 2002 4 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. the WM8739 and WM8739l (in both ssop and qfn packages) have been classified as msl1, which has an unlimited floor life at <30 c / 85% rh. condition min max digital supply voltage -0.3v +3.63v analogue supply voltage -0.3v +3.63 voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v master clock frequency 18.432mhz operating temperature range, t a -25 c+85 c storage temperature prior to soldering 30 c max / 85% rh max storage temperature after soldering -65 c +150 c package body temperature (soldering 10 seconds) +260 c package body temperature (soldering 2 minutes) +183 c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. the digital supply core voltage must always be less than or equal to the analogue supply voltage or digital supply buffer voltage. 3. the digital supply buffer voltage must always be less than or equal to the analogue supply voltage. recommended operating conditions C WM8739 parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.42 3.3 3.6 v digital supply range (buffer) dbvdd 2.7 3.3 3.6 v analogue supply range avdd 2.7 3.3 3.6 v ground dgnd,agnd 0 v recommended operating conditions C WM8739l parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.42 3.3 3.6 v digital supply range (buffer) dbvdd 1.8 3.3 3.6 v analogue supply range avdd 1.8 3.3 3.6 v ground dgnd,agnd 0 v
WM8739 / WM8739l production data w pd rev 3.1 december 2002 5 electrical characteristics C WM8739 test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 1.5v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit digital logic levels (cmos levels) input lowlevel v il 0.3 x vdd v input high level v ih 0.7 x vdd v output low v ol 0.1 x vdd v output high v oh 0.9 x vdd v analogue reference levels reference voltage v vmid avdd/2 v potential divider resistance r vmid 50k ohms power on reset threshold (dcvdd) dcvdd threshold on -> off v th 0.9 v hysteresis v ih 0.3 v dcvdd threshold off -> on v ol 0.6 v input to adc input signal level (0db) v inline 1.0 avdd/3.3 vrms a-weighted, 0db gain, fs = 48khz 85 90 a-weighted, 0db gain, fs = 96khz 90 signal to noise ratio (note 1,2) snr a-weighted, 0db gain, fs = 48khz, avdd = 2.7v 88 db dynamic range (note 2) dr a-weighted, -60db full scale input 85 90 db total harmonic distortion thd -1db input, 0db gain -84 0.006 -74 0.02 db % 1khz, 100mvpp 50 power supply rejection ratio psrr 20hz to 20khz 100mvpp 45 db adc channel separation 1khz input 90 db programmable gain 1khz input rsource < 50 ohms -34.5 0 +12 db programmable gain step size guaranteed monotonic 1.5 db mute attenuation 0db, 1khz input 80 db 0db gain 20k 30k input resistance r inline 12db gain 10k 15k ohms input capacitance c inline 10 pf
WM8739 / WM8739l production data w pd rev 3.1 december 2002 6 electrical characteristics C WM8739l all characteristics not repeated here are the same as for the WM8739. test conditions avdd, dbvdd = 1.8v, agnd = 0v, dcvdd = 1.5v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit input to adc a-weighted, 0db gain @ fs = 48khz 75 85 signal to noise ratio (note 1,2) snr a-weighted, 0db gain @ fs = 96khz 85 db dynamic range dr a-weighted, -60db full scale input 80 88 db total harmonic distortion thd -1db input, 0db gain -76 -60 db notes 1. ratio of output level with 1khz full scale input, to the output level with all zeros into the digital input over a 20hz to 20khz bandwidth using an audio analyser. 2. all performance measurements done with 20khz low pass filter, and where noted an a-weight filter. failure to use such a filter will result in higher thd+n and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 3. vmid decoupled with 10uf and 0.1uf capacitors (smaller values may result in reduced performance). terminology 1. signal-to-noise ratio (db) - snr is a measure of the difference in level between the full scale output and the output with a zero signal applied. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (db) - dnr is a measure of the difference between the highest and lowest portions of a signal. normally a thd+n measurement at 60db below full scale. the measured signal is then corrected by adding the 60db to it. (e.g. thd+n @ -60db= -32db, dr= 92db). 3. thd+n (db) - thd+n is a ratio, of the r.m.s. values, of (noise + distortion)/signal. 4. channel separation (db) - also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 7 power consumption C WM8739 current consumption typical mode description poweroff oscpd adcpd lineinpd avdd (3.3v) dcvdd (1.5v) dbvdd (3.3v) unit record oscillator enabled 0 0 0 0 9.2 2.6 0.8 ma using external clock 0 1 0 0 9.2 2.6 0.07 ma standby external clock still running 0 1 1 1 16 77 65 a clock stopped 0 1 1 1 16 0.3 0.2 a power down external clock still running 1111 0.2 77 65 a clock stopped 1 1 1 1 0.3 0.3 0.3 a power consumption C WM8739l current consumption typical mode description poweroff oscpd adcpd lineinpd avdd (1.8v) dcvdd (1.5v) dbvdd (1.8v) unit record oscillator enabled 0 0 0 0 3.9 2.4 0.8 ma standby clock stopped 0111 8 - - a power down clock stopped 1111 1 - - a table 1 powerdown mode current consumption examples notes 1. t a =+25 o c, fs = 48khz, xti/mclk = 256fs (12.288mhz). 2. all figures are quiescent, with no signal. 3. the data presented here was measured with the audio interface in master mode whenever the internal clock oscillator was used, and in slave mode whenever an external clock was used (i.e. ms = 1 when oscpd = 0 and vice versa). however, it is also possible to use the WM8739/l with ms = oscpd = 0 or ms = oscpd = 1.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 8 digital audio interface timing xti/mclk t xtil t xtih t xtiy figure 1 system clock timing requirements test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a =+25 o c, slave mode fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit system clock timing information xti/mclk system clock pulse width high t xtih 20 ns xti/mclk system clock pulse width low t xtil 20 ns xti/mclk system clock cycle time t xtiy 50 ns bclk adcdat adclrc WM8739 adc dsp encoder figure 2 master mode connection bclk (output) adcdat adclrc (output) t dl t dda figure 3 digital audio data timing C master mode
WM8739 / WM8739l production data w pd rev 3.1 december 2002 9 test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information adclrc propagation delay from bclk falling edge t dl 010ns adcdat propagation delay from bclk falling edge t dda 010ns bclk adcdat adclrc WM8739 adc dsp encoder figure 4 slave mode connection bclk adclrc t bch t bcl t bcy adcdat t lrsu t lrh t dd figure 5 digital audio data timing C slave mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns adclrc set-up time to bclk rising edge t lrsu 10 ns adclrc hold time from bclk rising edge t lrh 10 ns adcdat propagation delay from bclk falling edge t dd 010ns
WM8739 / WM8739l production data w pd rev 3.1 december 2002 10 mpu interface timing csb sclk sdin t csl t dho t dsu t csh t scy t sch t scl t scs lsb t css figure 6 program register input timing C 3-wire mpu serial control mode test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sclk rising edge to csb rising edge t scs 500 ns sclk pulse cycle time t scy 80 ns sclk pulse width low t scl 20 ns sclk pulse width high t sch 20 ns sdin to sclk set-up time t dsu 20 ns sclk to sdin hold time t dho 20 ns csb pulse width low t csl 20 ns csb pulse width high t csh 20 ns csb rising to sclk rising t css 20 ns sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 7 program register input timing C 2-wire mpu serial control mode
WM8739 / WM8739l production data w pd rev 3.1 december 2002 11 test conditions avdd, dbvdd = 3.3v, agnd = 0v, dcvdd = 3.3v, dgnd = 0v, t a =+25 o c, slave mode, fs = 48khz, xti/mclk = 256fs unless otherwise stated. parameter symbol test conditions min typ max unit program register input information sclk frequency 0 400 khz sclk low pulse-width t 1 600 ns sclk high pulse-width t 2 1.3 us hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns
WM8739 / WM8739l production data w pd rev 3.1 december 2002 12 device description introduction the WM8739 is a low power analogue to digital converter (adc) designed for audio recording. its features, performance and low power consumption make it ideal for recordable cd players, mp3 players and portable mini-disc players. the device includes programmable level line inputs, a crystal oscillator, configurable digital audio interface and a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and dsps. the WM8739 has low noise line inputs with programmable +12db to C34.5db logarithmic volume adjustments and mute. the adc is of a high quality using a multi-bit high-order oversampling architecture delivering optimum performance with low power consumption. the output from the adc is available on the digital audio interface. the adc includes a digital high pass filter to remove unwanted dc components from the audio signal. the design of the WM8739 has given much attention to power consumption without compromising performance. it includes the ability to power off parts of the circuitry under software control, including a standby and power off mode. the device caters for a number of different sampling rates including industry standard 8khz, 32khz, 44.1khz, 48khz, 88.2khz and 96khz. there are two unique schemes featured within the programmable sample rates of the WM8739: normal industry standard 256/384 fs sampling mode may be used. a special usb sampling mode is also included, whereby all audio sampling rates can be generated from a 12.00mhz usb clock. the WM8739s unique sample rate converter thus allows the user to generate the required sampling rate clocks from the 12mhz usb clock. the digital filters used for recording are optimised for each sampling rate used. the digitised output is available in a number of audio data formats i 2 s, dsp mode (a burst mode in which frame sync plus 2 data packed words are transmitted), msb-first, left justified and msb-first, right justified. the digital audio interface can operate in both master or slave modes. the WM8739 can generate the system master clock using an on-chip crystal oscillator, or alternatively it can accept an external master clock from the audio system. all features are software controlled using either a 2 or 3-wire mpu interface. line inputs the WM8739 provides left and right channel line inputs (rlinein and llinein). the inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi and other audio equipment. both line inputs include independent programmable volume level adjustments and mutes. the scheme is illustrated in figure 8. passive rf and active anti-alias filters are also incorporated within the line inputs. these prevent high frequencies aliasing into the audio band or otherwise degrading performance.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 13 12.5k vmid linein to adc figure 8 line input schematic line input schematic the gain between the line inputs and the adc is logarithmically adjustable from +12db to C34.5db in 1.5db steps under software control. the adc full scale input is 1.0v rms at avdd = 3.3 volts. any voltage greater than full scale will possibly overload the adc and cause distortion. note that the full scale input tracks directly with avdd. the gain is independently adjustable on both right and left line inputs. however, by setting the inboth bit whilst programming the volume control, both channels are simultaneously updated. use of inboth reduces the required number of software writes required. the line inputs can be muted in the analogue domain under software control. the software control registers are shown below. register address bit label default description 4:0 linvol[0:4] 10111 ( 0db ) left channel line input volume control 11111 = +12db . . 1.5db steps down to 00000 = -34.5db 7 linmute 1 left channel line input mute 1 = enable mute 0 = disable mute 0000000 left line in 8 lrinboth 0 left to right channel line input volume and mute data load control 1 = enable simultaneous load of linvol[0:4] and linmute to rinvol[0:4] and rinmute 0 = disable simultaneous load 4:0 rinvol[0:4] 10111 ( 0db ) right channel line input volume control 11111 = +12db . . 1.5db steps down to 00000 = -34.5db 7 rinmute 1 left channel line input mute 1 = enable mute 0 = disable mute 0000001 right line in 8 rlinboth 0 right to left channel line input volume and mute data load control 1 = enable simultaneous load of rinvol[0:4] and rinmute to linvol[0:4] and linmute 0 = disable simultaneous load table 2 line input software control
WM8739 / WM8739l production data w pd rev 3.1 december 2002 14 the line inputs are biased internally through the operational amplifier to vmid. whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to vmid using special anti-thump circuitry. this reduces any audible clicks that may otherwise be heard when re-activating the inputs. the external components required to complete the line input application are shown in the figure 9. agnd agnd r1 r2 c1 c2 agnd linein figure 9 line input application drawing for interfacing to a typical cd system, it is recommended that the input is scaled to ensure that there is no clipping at the input. r1 = 5k, r2= 5k, c1=47pf, c2=470nf (10v ceramic type). r1 and r2 form a resistive divider to attenuate the 2 vrms output from a cd player to a 1 vrms level, so avoiding overloading the inputs. r2 also provides a discharge path for c2, thus preventing the input to c2 charging to an excessive voltage which may otherwise damage any equipment connected that is not suitably protected against high voltages. c1 forms an rf low pass filter for increasing the rejection of rf interference picked up on any cables. c2 forms a dc blocking capacitor to remove the dc path between the WM8739 and the driving audio equipment. c2 together with the input impedance of the WM8739 form a high pass filter. adc the WM8739 uses a multi-bit oversampled sigma-delta adc. a single channel of the adc is illustrated in the figure 10. analog integrator from line input multi bits to adc digital filters figure 10 multi-bit oversampling sigma delta adc schematic the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 15 the adc full scale input is 1.0v rms at avdd = 3.3 volts. any voltage greater than full scale will possibly overload the adc and cause distortion. note that the full scale input tracks directly with avdd. the device employs a pair of adcs. the two channels cannot be selected independently. the digital data from the adc is fed for signal processing to the adc filters. adc filters the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. figure 11 illustrates the digital filter path. from adc digital hpf digital filter to digital audio interface digital decimator hpfen figure 11 adc digital filter adc digital filter the adc digital filters contain a digital high pass filter, selectable via software control. the high-pass filter response is detailed in the digital filter characteristics section. when the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. by setting hpor the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. if the dc offset changed, the stored and subtracted value will not change unless the high-pass filter is enabled. the software control is shown in table 3. register address bit label default description 0 adchpd 0 adc high pass filter enable (digital) 1=disablehighpassfilter 0 = enable high pass filter 0000101 audio path control 4 hpor 0 store dc offset when high pass filter disabled 1=storeoffset 0 = clear offset table 3 adc software control there are several types of adc filter, the frequency and phase responses of which are shown in digital filter characteristics. the filter types are automatically configured depending on the sample rate chosen. refer to the sample rate section for more details. clocking schemes in a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio systems master clock. to allow WM8739 to be used in a centrally clocked system, the WM8739 is capable of either generating this system clock itself or receiving it from an external source as will be discussed. for applications where it is desirable that the WM8739 is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the xti/mclk input and xto output pins (see crystal oscillator section).
WM8739 / WM8739l production data w pd rev 3.1 december 2002 16 for applications where a component other than the WM8739 will generate the reference clock, the external system can be applied directly through the xti/mclk input pin with no software configuration necessary. note that in this situation, the oscillator circuit of the WM8739 can be safely powered down to conserve power (see power down section) crystal oscillator the WM8739 includes a crystal oscillator circuit that allows the audio systems reference clock to be generated on the device. the crystal oscillator is a low radiation type, designed for low emc. a typical application circuit is shown in figure 12. xti/mclk xto dgnd dgnd cp cp figure 12 crystal oscillator application circuit for crystals with a 30pf fundamental load capacitance, a value of 5pf for cp is recommended. the WM8739 crystal oscillator provides an extremely low jitter clock source. low jitter clocks are a requirement for a high quality audio adc, regardless of the converter architecture. the WM8739 architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. in applications where there is more than one source for the master clock, it is recommended that the clock is generated by the WM8739 to minimise such problems. core clock the WM8739 dsp core can be clocked either by mclk or mclk divided by 2. this is controlled by software as shown in table 4 below. register address bit label default description 0001000 sampling control 6 clkidiv2 0 core clock divider select 1 = core clock is mclk divided by 2 0 = core clock is mclk table 4 software control of core clock having a programmable mclk divider allows the device to be used in applications where higher frequency master clocks are available. for example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. digital audio interfaces WM8739 may be operated in either one of the 4 offered audio interface modes. these are: ? right justified ? left justified ? i 2 s ? dsp mode all four of these modes are msb first.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 17 the digital audio interface takes the data from the internal adc digital filters and places it on adcdat and adclrc. adcdat is the formatted digital audio data stream output from the adc digital filters with left and right channels multiplexed together. adclrc is an alignment clock that controls whether left or right channel data is present on the adcdat line. adcdat and adclrc are synchronous with the bclk signal with each data bit transition signified by a bclk high to low transition. adcdat is always an output. bclk and adclrc maybe an input or an output depending whether the device is in master or slave mode. refer to the master/slave operation section. there are four digital audio interface formats accommodated by the WM8739. these are shown in the figures below. refer to the electrical characteristic section for timing information. left justified mode is where the msb is available on the first rising edge of bclk following a adclrc transition. left channel right channel adclrc bclk adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 13 left justified mode i 2 s mode is where the msb is available on the 2nd rising edge of bclk following an adclrc transition. left channel right channel adclrc bclk adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb 1bclk 1bclk figure 14 i 2 smode right justified mode is where the lsb is available on the rising edge of bclk preceding an adclrc transition, yet msb is still transmitted first.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 18 left channel right channel adclrc bclk adcdat 1/fs n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 lsb msb figure 15 right justified mode dsp mode is where the left channel msb is available on either the 1 st or 2 nd rising edge of bclk (selectable by lrp) following a adclrc transition high. right channel data immediately follows left channel data. left channel right channel adclrc bclk adcdat n 3 2 1 n-2 n-1 lsb msb n 3 2 1 n-2 n-1 1bclk input word length (iwl) note: input word length is defined by the iwl register, lrp = 1 1/fs figure 16 dsp mode the adc digital audio interface modes are software configurable as indicated in figure 16. note that dynamically changing the software format may results in erroneous operation of the interfaces and is therefore not recommended. the length of the digital audio data is programmable at 16/20/24 or 32 bits. refer to the software control table below. the data is signed 2s complement. the adc digital filters process data using 24 bits. if the adc is programmed to output 16 or 20 bit data then it strips the lsbs from the 24 bit data. if the adc is programmed to output 32 bits then it packs the lsbs with zeros. adcdat is always an output. it powers up and returns from standby low. adclrc and bclk can be either outputs or inputs depending on whether the device is configured as a master or slave. if the device is a master then the adclrc and bclk signals are outputs that default low. if the device is a slave then the adclrc and bclk are inputs.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 19 register address bit label default description 1:0 format[1:0] 10 audio data format select 11 = dsp mode, frame sync + 2 data packed words 10 = i 2 s format, msb-first left-1 justified 01 = msb-first, left justified 00 = msb-first, right justified 3:2 iwl[1:0] 10 input audio data bit length select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 lrp 0 dsp mode a/b select (in dsp mode only) 1 = msb is available on 2nd bclk rising edge after lrc rising edge 0 = msb is available on 1st bclk rising edge after lrc rising edge 0000111 digital audio interface forma t 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode table 5 digital audio interface control note: right justified 32 bit mode is not supported, but if selected, will put the WM8739 into 24 bit right justified mode. master and slave mode operation the WM8739 can be configured as either a master or slave mode device. as a master mode device the WM8739 controls sequencing of the data and clocks on the digital audio interface. as a slave device the WM8739 responds with data to the clocks it receives over the digital audio interface. the mode is set with the ms bit of the control register as shown in table 6. register address bit label default description 0000111 digital audio interface format 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode table 6 programming master/slave modes as a master mode device the WM8739 controls the sequencing of data transfer (adcdat) and output of clocks (bclk, adclrc) over the digital audio interface. it uses the timing generated from either its on-board crystal or the mclk input as the reference for the clock and data transitions. this is illustrated in figure 17. adcdat is always an output from the WM8739 independent of master or slave mode.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 20 bclk adcdat adclrc WM8739 adc dsp encoder figure 17 master mode as a slave device the WM8739 sequences the data transfer (adcdat) over the digital audio interface in response to the external applied clocks (bclk, adclrc). this is illustrated figure 18. bclk adcdat adclrc WM8739 adc dsp encoder figure 18 slave mode audio data sampling rates the WM8739 provides for two modes of operation (normal and usb) to generate the required adc sampling rate. normal and usb modes are programmed under software control according to the table below. in normal mode, the user controls the sample rate by using an appropriate mclk or crystal frequency and the sample rate control register setting. the WM8739 can support sample rates from 8ks/s up to 96ks/s. in usb mode, the user must use a fixed mlck or crystal frequency of 12mhz to generate sample rates from 8ks/s to 96ks/s. it is called usb mode since the common usb (universal serial bus) clock is at 12mhz and the WM8739 can be directly used within such systems. WM8739 can generate all the normal audio sample rates from this one master clock frequency, removing the need for different master clocks or pll circuits.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 21 register address bit label default description 0 usb/ normal 0 mode select 1 = usb mode (250/272fs) 0 = normal mode (256/384fs) 1 bosr 0 base over-sampling rate usb mode 0 = 250fs 1 = 272fs normal mode 0 = 256fs 1 = 384fs 0001000 sampling control 5:2 sr[3:0] 0000 adc sample rate control; see usb mode and normal mode sample rate sections for operation table 7 sample rate control normal mode sample rates in normal mode mclk/crystal oscillator is set up according to the desired sample rate of the adc. for adc sampling rates of 8, 32, 48 or 96khz, mclk frequencies of either 12.288mhz (256fs) or 18.432mhz (384fs) can be used. for adc sampling rates of 8, 44.1 or 88.2khz from mclk frequencies of either 11.2896mhz (256fs) or 16.9344mhz (384fs) can be used. the table below should be used to set up the device to work with the various sample rate combinations. for example if the user wishes to use the WM8739 in normal mode with the adc sample rate at 48khz, then the device should be programmed with bosr = 0, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0 with a 12.288mhz mclk or with bosr = 1, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0 with a 18.432mhz mclk. the adc will then operate with a digital filter of type 1, refer to digital filter characteristics section for an explanation of the different filter types. sampling rate mclk frequency sample rate register settings digital filter type khz mhz bosr sr3 sr2 sr1 sr0 12.288 0 0 0 0 0 48 18.432 1 0 0 0 0 1 12.288 0 0 0 1 0 8 18.432 1 0 0 1 0 1 12.288 0 0 1 1 0 32 18.432 1 0 1 1 0 1 12.288 0 0 1 1 1 96 18.432 1 0 1 1 1 2 11.2896 0 1 0 0 0 44.1 16.9344 1 1 0 0 0 1 11.2896 0 1 0 1 0 8(note1) 16.9344 1 1 0 1 0 1 11.2896 0 1 1 1 1 88.2 16.9344 1 1 1 1 1 2 table 8 normal mode sample rate look-up table notes: 1. 8k not exact, actual = 8.018khz 2. all other combinations of bosr and sr[3:0] that are not in the truth table are invalid the bosr bit represents the base over-sampling rate. this is the rate that the WM8739 digital signal processing is carried out at. in normal mode, with bosr = 0, the base over-sampling rate is at 256fs, with bosr = 1, the base over-sampling rate is at 384fs. this can be used to determine the actual audio data rate produced by the adc.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 22 example scenarios are: 1. with a requirement that the adc data rate is 8khz, then choosing mclk = 12.288mhz the device is programmed with bosr = 0 (256fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0.the adc output data rate will then be exactly 8khz (derived from 12.288mhz/256 x1/6) 2. with a requirement that adc data rate is 8khz, then choosing mclk = 16.9344mhz the device is programmed with bosr = 1 (384fs), sr3 = 1, sr2 = 0, sr1 = 0, sr0 = 1. the adc will no longer output data at exactly 8.000khz, instead it will be 8.018khz (derived from 16.9344mhz/384 x 2/11). a slight (sub 0.5%) pitch shift will therefore result in the 8khz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018khz rate. the exact sample rates achieved are defined by the relationships in table 9. actual sampling rate bosr=0 (256fs) bosr=1 (384fs) target sampling rate mclk=12.288 mclk=11.2896 mclk=18.432 mclk=16.9344 khz khz khz khz khz 8 8.018 8 8.018 8 12.288mhz/256 x 1/6 11.2896mhz/256 x 2/11 18.432mhz/384 x 1/6 16.9344mhz/384 x 2/11 32 32 32 12.288mhz/256 x 2/3 not available 18.432mhz/384x 2/3 not available 44.1 44.1 44.1 not available 11.2896mhz/256 not available 16.9344mhz /384 48 48 48 12.288mhz/256 not available 18.432mhz/384 not available 88.2 88.2 88.2 not available 11.2896mhz/384 x 2 not available 16.9344mhz /384 x 2 96 96 96 12.288mhz/256 x 2 not available 18.432mhz/384 x 2 not available table 9 normal mode actual sample rates 128/192fs normal mode the normal mode sample rates are designed for standard 256fs and 384fs mclk rates. however the WM8739 is also capable of being clocked from a 128/192fs mclk for application over limited sampling rates as shown in the table below. sampling rate mclk frequency sample rate register settings digital filter type khz mhz bosr sr3 sr2 sr1 sr0 6.144 0 0 1 1 1 48 9.216 1 0 1 1 1 2 5.6448 0 1 1 1 1 44.1 8.4672 1 1 1 1 1 2 table 10 128/192fs normal mode sample rate look-up table 512/768fs normal mode 512fs and 768fs mclk rates can be accommodated by using the clkidiv2 bit. the core clock to the dsp will be divided by 2 so an external 512/768 mclk will become 256/384fs internally and the device otherwise operates as in table 8 but with mclk at twice the specified rate. see table 4 for software control.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 23 usbmode sample rates in usb mode the mclk/crystal oscillator input is 12mhz only. sampling rate mclk frequency sample rate register settings digital filter type khz mhz bosr sr3 sr2 sr1 sr0 48 12.000 0 0 0 0 0 0 44.1 (note 2) 12.000 1 1 0 0 0 1 8 12.000 0 0 0 1 0 0 8 (note 1) 12.000 1 1 0 1 0 1 32 12.000 0 0 1 1 0 0 96 12.000 0 0 1 1 1 3 88.2 (note 3) 12.000 1 1 1 1 1 2 table 11 usbmode sample rate look-up table notes: 1. 8k not exact, actual = 8.021khz 2. 44.1k not exact, actual = 44.118khz 3. 88.2k not exact, actual = 88.235khz 4. all other combinations of bosr and sr[3:0] that are not in the truth table are invalid the table above can be used to set up the device to work with various sample rate combinations. for example if the user wishes to use the WM8739 in usb mode with the adc sample rate at 48khz, then the device should be programmed with bosr = 0, sr3 = 0, sr2 = 0, sr1 = 0 and sr0 = 0. the adc will then operate with a digital filter of type 0, refer to digital filter characteristics section for an explanation of the different filter types. the bosr bit represents the base over-sampling rate. this is the rate that the WM8739 digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. in usb mode, with bosr = 0, the base over-sampling rate is defined at 250fs, with bosr = 1, the base over- sampling rate is defined at 272fs. this can be used to determine the actual audio sampling rate produced by the adc. example scenarios are: 1. with a requirement that the adc data sampling rate is 8khz the device is programmed with bosr = 0 (250fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0.the adc will then be exactly 8khz (derived from 12mhz/250 x 1/6). 2. with a requirement that adc data rate is 8khz the device is programmed with bosr = 1 (272fs), sr3 = 0, sr2 = 0, sr1 = 1, sr0 = 0. the adc will not output data at exactly 8khz, instead it will be 8.021khz (derived from 12mhz/272 x 2/11). a slight (sub 0.5%) pitch shift will therefore result in the 8khz audio data and (more importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.021khz rate.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 24 the exact sample rates supported for all combinations are defined by the relationships in table 12 below. actual sampling rate target sampling rate bosr=0 ( 250fs) bosr=1 (272fs) khz khz khz 8 8.021 8 12mhz/(250 x 48/8) 12mhz/(272 x 11/2) 32 32 12mhz/(250 x 48/32) not available 44.117 44.1 not available 12mhz/272 48 48 12mhz/250 not available 88.235 88.2 not available 12mhz/136 96 96 12mhz/125 not available table 12 usbmode actual sample rates activating dsp and digital audio interface to prevent any communication problems from arising across the digital audio interface the audio interface is disabled (tristate). once the audio interface and the sampling control has been programmed it is activated by setting the active bit under software control. register address bit label default description 0001001 active control 0 active 0 activate interface 1=active 0 = inactive table 13 activating dsp and digital audio interface it is recommended that between changing any content of digital audio interface or sampling control register that the active bit is reset then set. software control interface the software control interface may be operated using either a 3-wire or 2-wire mpu interface. selection of interface format is achieved by setting the state of the mode pin. in 3-wire mode, sdin is used for the program data, sclk is used to clock in the program data and csb is used to latch in the program data. in 2-wire mode, sdin is used for serial data and sclk is used for the serial clock. in 2-wire mode, the state of the csb pin allows the user to select one of two addresses. selection of serial control mode the serial control interface may be selected to operate in either 2 or 3-wire mode. this is achieved by setting the state of the mode pin. mode interface format 02wire 13wire table 14 control interface mode selection 3-wire serial control mode the WM8739 can be controlled using a 3-wire serial interface. sdin is used for the program data, sclk is used to clock in the program data and csb is used to latch in the program data. the 3-wire interface protocol is shown in figure 19.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 25 csb sclk sdin b15 b6 b7 b8 b9 b10 b11 b12 b13 b14 b1 b2 b3 b4 b5 b0 figure 19 3-wire serial interface notes: 1. b[15:9] are control address bits 2. b[8:0] are control data bits 2-wire serial control mode the WM8739 supports a 2-wire mpu serial interface. the device operates as a slave device only. the WM8739 has one of two slave addresses that are selected by setting the state of pin 20, (csb). sdin sclk ack r addr ack data b15-8 stop start data b7-0 r/w ack figure 20 2-wire serial interface notes: 1. b[15:9] are control address bits 2. b[8:0] are control data bits csbstate (default = low) address 0 0011010 1 0011011 table 15 2-wire mpu interface address selection to control the WM8739 on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on sdin while sclk remains high. this indicates that an address and data transfer will follow. all peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + r/wbit). the transfer is msb first. the 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see table 15). if the correct address is received and the r/w bit is 0, indicating a write, then the WM8739 will respond by pulling sdin low on the next clock pulse (ack). the WM8739 is a write only device and will only respond to the r/w bit indicating a write. if the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. once the WM8739 has acknowledged a correct address, the controller will send eight data bits (bits b[15]-b[8]). WM8739 will then acknowledge the sent data by pulling sdin low for one clock pulse. the controller will then send the remaining eight data bits (bits b[7]-b[0]) and the WM8739 will then acknowledge again by pulling sdin low. a stop condition is defined when there is a low to high transition on sdin while sclk is high. if a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 26 after receiving a complete address and data sequence the WM8739 returns to the idle state and waits for another start condition. each write to a register requires the complete sequence of start condition, device address and r/wbit followed by the 16 register address and data bits. power down modes the WM8739 contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. this is software programmable as shown in the table below. register address bit label default description 0 lineinpd 1 line input power down 1 = enable power down 0 = disable power down 2 adcpd 1 adc power down 1 = enable power down 0 = disable power down 5 oscpd 0 oscillator power down 1 = enable power down 0 = disable power down 0000110 power down control 7 poweroff 1 power off device 1=devicepoweroff 0=devicepoweron table 16 power conservation modes software control unused register bits 1,3,4,6 should be set to 1 when writing to this register. the power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. please follow the special instructions below if dynamic implementations are being used. oscpd: powers off the on board crystal oscillator. the mclk input will function independently of the oscillator being powered down. the device can be put into a standby mode (standby) by powering down all the audio circuitry under software control as shown in table 17. poweroff oscpd adcpd lineinpd description 001 1 standby, but with crystal oscillator 011 1 standby, crystal oscillator not-available. table 17 standby mode in standby mode the control interface, a small portion of the digital and areas of the analogue circuitry remain active. the active analogue includes the analogue vmid reference so that the analogue line inputs remain biased to vmid. this reduces any audible effects caused by dc glitches when entering or leaving standby mode.
WM8739 / WM8739l production data w pd rev 3.1 december 2002 27 the device can be powered off by writing to the poweroff bit of the power down register. in poweroff mode the control interface and a small portion of the digital remain active. the analogue vmid reference is disabled. as in standby mode the crystal oscillator pin can be independently controlled. refer to table 18. poweroff oscpd adcpd lineinpd description 10x x poweroff, but with crystal oscillator osc available 11x x poweroff, crystal oscillator not-available table 18 power off mode device resetting the WM8739 contains a power on reset circuit that resets the internal state of the device to a known condition. the power on reset is applied as dcvdd powers on and released only after the voltage level of dcvdd crosses a minimum turn off threshold. if dcvdd later falls below a minimum turn on threshold voltage then the power on reset is re-applied. the threshold voltages and associated hysteresis are shown in the electrical characteristics table. the user also has the ability to reset the device to a known state under software control as shown in the table below. register address bit label default description 0001111 reset register 8:0 reset not reset reset register writing 00000000 to register resets device table 19 software control of reset when using the software reset. in 3-wire mode the reset is applied on the rising edge of csb and released on the next rising edge of sclk. in 2-wire mode the reset is applied for the duration of the ack signal (approximately 1 sclk period, refer to figure 20).
WM8739 / WM8739l production data w pd rev 3.1 december 2002 28 register map the complete register map is shown in table 20. the detailed description can be found in the relevant text of the device description. there are 8 registers with 9 bits per register. these can be controlled using either the 2 wire or 3 wire mpu interface. register b 15 b 14 b 13 b 12 b 11 b 10 b9b8b7b6b5b4b3b2b1b0 r0 (00h) 0 0 0 0 0 0 0 lrin both lin mute 00 linvol r1 (02h) 0 0 0 0 0 0 1 rlin both rin mute 00 rinvol r5 (0ah) 0 0 0 0 1 0 10 0 0 0hpor0 0 0 adc hpd r6 (0ch) 0 0 0 0 1 1 00 pwr off 1 oscpd 1 1 adcpd 1 linein pd r7 (0eh) 0 0 0 0 1 1 10 0ms0lrp iwl format r8 (10h) 0 0 0 1 0 0 00 0 clki div2 sr bosr usb/ norm r9 (12h) 0 0 0 1 0 0 100000000activ e r15(1eh) 0 0 0 1 1 1 1 reset address data register address bit label default description 4:0 linvol[0:4] 10111 ( 0db ) left channel line input volume control 11111 = +12db . . 1.5db steps down to 00000 = -34.5db 7 linmute 1 left channel line input mute 1 = enable mute 0 = disable mute 0000000 left line in 8 lrinboth 0 left to right channel line input volume and mute data load control 1 = enable simultaneous load of linvol[0:4] and linmute to rinvol[0:4] and rinmute 0 = disable simultaneous load 4:0 rinvol[0:4] 10111 ( 0db ) right channel line input volume control 11111 = +12db . .1.5db steps down to 00000 = -34.5db 7 rinmute 1 left channel line input mute 1 = enable mute 0 = disable mute 0000001 right line in 8 rlinboth 0 right to left channel line input volume and mute data load control 1 = enable simultaneous load of rinvol[0:4] and rinmute to linvol[0:4] and linmute 0 = disable simultaneous load
WM8739 / WM8739l production data w pd rev 3.1 december 2002 29 register address bit label default description 0 adchpd 0 adc high pass filter enable (digital) 1=disablehighpassfilter 0 = enable high pass filter 0000101 digital audio path control 4 hpor 0 store dc offset when high pass filter disabled 1=storeoffset 0 = clear offset 0 lineinpd 1 line input power down 1 = enable power down 0 = disable power down 2 adcpd 1 adc power down 1 = enable power down 0 = disable power down 5 oscpd 0 oscillator power down 1 = enable power down 0 = disable power down 0000110 power down control 7 poweroff 1 poweroff mode 1 = enable poweroff 0=disablepoweroff 1:0 format[1:0] 10 audio data format select 11 = dsp mode, frame sync + 2 data packed words 10 = i 2 s format, msb-first left-1 justified 01 = msb-first, left justified 00 = msb-first, right justified 3:2 iwl[1:0] 10 input audio data bit length select 11 = 32 bits 10 = 24 bits 01 = 20 bits 00 = 16 bits 4 lrp 0 dsp mode a/b select (in dsp mode only) 1 = msb is available on 2nd bclk rising edge after lrc rising edge 0 = msb is available on 1st bclk rising edge after lrc rising edge 0000111 digital audio interface format 6 ms 0 master slave mode control 1 = enable master mode 0 = enable slave mode 0 usb/ normal 0 mode select 1 = usb mode (250/272fs) 0 = normal mode (256/384fs) base over-sampling rate 1bosr 0 usb mode 0 = 250fs 1 = 272fs normal mode 0 = 256fs 1 = 384fs 5:2 sr[3:0] 0000 (fs) adc sample rate control; see usb mode and normal mode sample rate sections for operation 0001000 sampling control 6 clkidiv2 0 core clock divider select 1 = core clock is mclk divided by 2 0=coreclockismclk
WM8739 / WM8739l production data w pd rev 3.1 december 2002 30 register address bit label default description 0001001 active control 0 active 0 activate interface 1=active 0 = inactive 0001111 reset register 8:0 reset not reset reset register write 000000000 to register triggers reset table 20 register map description note 1. all other bits not explicitly defined in the register table should be set to zero, unless specified otherwise (see powerdown section). digital filter characteristics the adc employs different digital filters. there are 4 types of digital filter, called type 0, 1, 2 and 3. the performance of types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages. parameter test conditions min typ max unit adc filter type 0 (usbmode, 250fs operation) +/- 0.05db 0 0.416fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.584fs stopband attenuation f > 0.584fs -60 db adc filter type 1 (usbmode, 272fs or normal mode operation) +/- 0.05db 0 0.4535fs passband -6db 0.5fs passband ripple +/- 0.05 db stopband 0.5465fs stopband attenuation f > 0.5465fs -60 db high pass filter corner frequency -3db -0.5db -0.1db 3.7 10.4 21.6 hz table 21 digital filter characteristics terminology 1. stop band attenuation (db) - the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple C any variation of the frequency response in the pass-band region
WM8739 / WM8739l production data w pd rev 3.1 december 2002 31 adc filter responses -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 21 adc digital filter frequency response Ctype 0 figure 22 adc digital filter ripple Ctype 0 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 response (db) frequency (fs) figure 23 adc digital filter frequency response Ctype 1 figure 24 adc digital filter ripple Ctype 1 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 25 adc digital filter frequency response Ctype 2 figure 26 adc digital filter ripple Ctype 2
WM8739 / WM8739l production data w pd rev 3.1 december 2002 32 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 response (db) frequency (fs) -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0 0.05 0.1 0.15 0.2 0.25 response (db) frequency (fs) figure 27 adc digital filter frequency response Ctype 3 figure 28 adc digital filter ripple Ctype 3 adchighpassfilter the WM8739 has a selectable digital high pass filter to remove dc offsets. the filter response is characterised by the following polynomial. h(z) = 1 C z -1 1 C 0.9995 z -1
WM8739 / WM8739l production data w pd rev 3.1 december 2002 33 recommended external components audio serial data i/f 3-wire interface 2-wire interface WM8739 adc vmid avdd agnd 14 15 3.3v 0.1 f 10 f + 16 adclrc adcdat dbvdd dcvdd 3.3v dgnd 1.5v - 3.3v + + 7 6 5 bclk 8 12 11 sdin 1 csb 19 sclk 20 mode 2 10 f0.1 f xto xti/mclk 15pf 15pf 4 3 + 10 f rlinein 5k ? 5k ? 47pf + 470nf 17 llinein 5k ? 5k ? 47pf + 470nf 18 0.1 f 10 f 0.1 f 3-wire or 2-wire mpu interface 10k ? 3.3v notes: 1. agnd and dgnd should be connected as close to the WM8739 as possible. 2. 0.1 f capacitors should be positioned as close the the WM8739 as possible. 3. capacitor types should be carefully chosen. capacitors with very low esr are recommended for optimum performance. figure 29 external components diagram
WM8739 / WM8739l production data w pd rev 3.1 december 2002 34 package dimensions (ssop) notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.20mm. d. meets jedec.95 mo-150, variation = ae. refer to this specification for further details. dm0015.b ds: 20 pin ssop (7.2 x 5.3 x 1.75 mm) symbols dimensions (mm) min nom max a ----- ----- 2.0 a 1 0.05 ----- ----- a 2 1.65 1.75 1.85 b 0.22 0.30 0.38 c 0.09 ----- 0.25 d 6.90 7.20 7.50 e 0.65 bsc e 7.40 7.80 8.20 5.00 5.30 5.60 l 0.55 0.75 0.95 ref: a a2 a1 seating plane -c- 0.10 c 10 1 d 11 20 e b e1 e - jedec.95, mo 150 0 o 4 o 8 o e 1 l 1 0.125 ref c l gauge plane 0.25 l 1
WM8739 / WM8739l production data w pd rev 3.1 december 2002 35 package dimensions (qfn) notes: 1. dimension b applied to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. dimension l1 represents terminal pull back from package side wall. maximum of 0.1mm is acceptable. where terminal pull back exists, only upper half of lead is visible on package side wall due to half etching of leadframe. 2. falls within jedec, mo-220 with the exception of d2, e2: d2,e2: larger pad size chosen which is just outside jedec specification 3. all dimensions are in millimetres 4. this drawing is subject to change without notice. 5. shape and size of corner tie bar may vary with package terminal count. corner tie bar is connected to exposed pad internally dm023.d fl: 28 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch c aaa index area (d/2 x e/2) c aaa 2x 2x top view d e c 0.08 c ccc a a1 c (a3) seating plane 1 14 13 b 15 l d2/2 d2 e2 e2/2 see detail b b c ccc m a b b a a 27 28 1 2 7 8 21 22 e 5 corner tie bar detail a b c bbb m a 28x b l 28x k l1 r 1 1 0. 566 mm 5 corner tie bar 0 . 1 5 detail b terminal tip r datum e e/2 l1 1 see detail a symbols dimensions (mm) min nom max note a a1 a3 b d d2 e e2 e l l1 r 0.85 0.90 1.00 0.05 0.02 0 0.2 ref 0.30 0.23 0.18 5.00 bsc 3.4 3.3 3.2 5.00 bsc 0.5 bsc 3.3 3.4 3.2 0.35 0.4 0.45 0.1 b(min)/2 1 2 2 1 k 0.20 aaa bbb ccc ref: 0.15 0.10 0.10 jedec, mo-220, variation vkkd-2 tolerances of form and position exposed centre pad
WM8739 / WM8739l production data w pd rev 3.1 december 2002 36 important notice wolfson microelectronics plc (wm) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. all products are sold subject to the wm terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. wm warrants performance of its products to the specifications applicable at the time of sale in accordance with wms standard warranty. testing and other quality control techniques are utilised to the extent wm deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. in order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. wm assumes no liability for applications assistance or customer product design. wm does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of wm covering or relating to any combination, machine, or process in which such products or services might be or are used. wms publication of information regarding any third partys products or services does not constitute wms approval, license, warranty or endorsement thereof. reproduction of information from the wm web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. representation or reproduction of this information with alteration voids all warranties provided for an associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. resale of wms products or services with statements different from or beyond the parameters stated by wm for that product or service voids all express and any implied warranties for the associated wm product or service, is an unfair and deceptive business practice, and wm is not responsible nor liable for any such use. address: wolfson microelectronics plc 20 bernard terrace edinburgh eh8 9nx united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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